The present invention relates to a two-wire communication protocol between a controller device and a controlled device. The invention more particularly relates to digitally trimmable electronic devices such as a capacitor, a potentiometer, a current source, or other variable impedance elements.
Both controller and controlled devices are coupled by a clock line and a data line. The controller device sends control signals comprising N bits, N being greater than or equal to two, to the controlled device on the data line.
In the prior art, the document U.S. Pat. No. 5,084,667 discloses a variable impedance circuit for incorporation into electronic circuits in place of a potentiometer or similar mechanical variable impedance element. The impedance of the impedance circuit is set by electrical signals sent thereto. Once set, the impedance value is stored in a programmable non-volatile read only memory. When power is restored, this stored impedance value is re-established.
FIG. 1 is a block diagram of the impedance circuit according to this document. The variable impedance circuit 1 consists of an impedance network 2 which consists of a number of fixed impedance elements and switches which are not shown. The switches are used to connect various combinations of impedance elements between two terminals 3 and 4. The particular combination is determined by a value stored in a control circuit which is counter 5. The count stored in the counter may be altered by signals on two lines 6 and 7. The Up/Down (U/D) signal on line 6 determines whether counter 5 will be incremented or decremented by a predetermined amount in response to an increment (INC) signal on line 7.
A third signal line 8 which is referred to as chip select (CS) line 8 is used as an activation signal for counter 5. When chip select line 8 is low, counter 5 responds to signals on lines 6 and 7. This enables the circuit controlling the variable impedance circuit 1 to alter the value stored in counter 5. This controlling circuit causes chip select line 8 to go low. It then couples the appropriate signals to counter 5 on lines 6 and 7 to cause the value stored in counter 5 to change to the new desired value.
FIG. 2 is an array of the selection mode of the variable impedance circuit. When the CS line is low, the value stored in the counter may be altered. On the falling edge of the INC line, the counter is incremented if the U/D line is high and decremented if U/D line is low.
Such a variable impedance circuit has some drawbacks. First, two lines INC and U/D are used to allow only two control signals for the counter, an increment and a decrement signal. Further, with these two lines INC and U/D no start and end signals are available. This is why it is provided with a third line CS which determines by its level whether the value stored in the counter is alterable or not. To implement such a solution, it is necessary to have an additional terminal on the circuit.
In the prior art, the document WO 01/76069 discloses a method of electronically adjusting electrical capacitors which may be variably set or trimmed to a desired value of capacitance.
FIG. 3 is a block diagram illustrating the electronic trim capacitor 10 which is implemented as a digitally programmable capacitance 11. The electronic trim capacitor 10 has a first power terminal 12 (Vdd) and a second power terminal 13 (Vss); a first capacitor terminal 14 (C1) and a second capacitor terminal 15 (C2); a program terminal 16 (PROGRAM); and an enable terminal 17 (ENABLE). The first power terminal 12 and the second power terminal 13 may receive suitable electrical power to operate the electronic trim capacitor 10. Also, the first capacitor terminal 14 and the second capacitor terminal 15 connect the electronic trim capacitor 10 to a general circuit (not shown) which requires capacitive adjustment such as an amplifier or an oscillator. The program terminal 16 and the enable terminal 17 here provide the ability to digitally program the electronic trim capacitor 10 to a desired specific value of capacitance.
The programming method used with the electronic trim capacitor 10 comprises the following main steps. In an initial step, programming is initiated by setting the enable terminal 17 to a particular electrical state.
In a following step, programming continues by supplying an appropriate pulse signal to the program terminal 16. In this manner, supplying a selected number of pulses in the pulse signal, while the enable terminal 17 is enabled, will produce a desired total number of capacitance increments in the electronic trim capacitor 10.
Finally in another step, the internal logic of the electronic trim capacitor 10 sets a capacitive value which is exhibited at the first capacitor terminal 12 and the second capacitor terminal 13.
Such an electronic trim capacitor also has some drawbacks. After setting the enable terminal in order to activate the electronic trim capacitor, only an increment function is provided. With only one control signal available, there is no freedom to modify the value of the capacitance or to monitor this value. Further, if a decrement operation is requested or if the desired value is less than the current value of the electronic trim capacitor, it is necessary to provide with a reset terminal to reset the capacitance value or a mechanism which resets the capacitance value to zero when the maximum value is reached by successive increment signals. In both cases it is not worthy, the first alternative requires an additional terminal and the second one takes too much time.